As is known, there exists a demand from the market for EEPROM memory devices of ever larger capacity (&gt;256 Kb), which implies a demand for physically ever smaller memory cells and hence increased difficulty in fabricating such cells.
Memory devices of the FLOTOX EEPROM type are presently the most widely employed memory devices by major manufacturers throughout the world. These devices are formed of floatinggate memory cells with two levels of polysilicon, wherein an electric charge is stored to establish two different cell states, "written or "erased," which correspond to the logic states of "1" or "0", respectively.
More particularly, FIGS. 1 and 2 show the details of a FLOTOX EEPROM type of memory cell, indicated at 1, which is included in a memory device 2, itself formed on a semiconductor material substrate 10 having a first conductivity type, specifically of the P type. The device 2 further comprises a select transistor 3 connected in series with the cell 1.
Referring now to FIG. 1, it can be seen that the substrate 10 includes a source region 11 of the cell 1 which has a second conductivity type, specifically of the N type, and a region 12 of electric continuity having the same conductivity type. This substrate also includes a drain region 13 of the cell 1 and a source region of the transistor 3 (the drain/source region 13) having the second conductivity type, specifically of the N type. All the regions indicated at 11-14 are facing a surface 15 of the substrate 10.
With further reference to FIG. 1, in stacked arrangement above the surface 15 are the following: a gate oxide region 18 of the cell 1, at the sides whereof are the source 11 and drain 13 regions of the cell, the region 18 having a thin tunnel oxide region 19 formed therein, a first portion 20 of a first polycrystalline silicon (poly1) layer, a first portion 21 of a dielectric (interpoly) layer, and a first portion 22 of a second (poly2) layer comprised of polycrystalline silicon and tungsten silicide. The portions 20 and 22 form the floating gate region and control gate region, respectively, of the cell 1.
A portion of the substrate 10, indicated at 31 in FIG. 1, is included between the region 12 of electric continuity and the source region 11 of the cell 1 to form the cell channel region having a length dimension denoted by L.
It should be noted that the thin tunnel oxide region 19, provided thinner (approximately 80 .ANG. thick) than the gate oxide region 18, is adapted to pass electric charges to the floating gate region by tunnel effect (a phenomenon also known as Fowler-Nordheim current), i.e., for programming the cell 1.
The region 12 of electric continuity, formed laterally and beneath the thin tunnel oxide region 19 and partly overlapping the drain region 13 of the cell 1, provides electric continuity between a portion of the substrate 10 underlying the region 19 (the so-called tunnel area) and the drain region 13.
With continued reference to FIG. 1, stacked on top of one another above the surface 15 are: a gate oxide region 25 of the select transistor 3, at the sides whereof there extend the source 13 and drain 14 transistor regions, a second portion 26 of poly1, a second portion 27 of the dielectric (interpoly) layer, and a second portion 28 of poly2. The portions 26 and 28 of the polycrystalline silicon layer are shortcircuited to a field oxide region, not shown in the drawings, outside the cell 1. An intermediate oxide layer 30 covers the device 2 and isolates the various layers from one another.
As can be seen in FIG. 2, the floating gate region, portion 20 of poly1, of the cell 1 is insulated and enclosed at the top and the sides by the dielectric interpoly layer 21, preferably an ONO layer formed of a superposition of silicon Oxide-silicon Nitride-silicon Oxide, and at the bottom by the gate oxide 18 and tunnel oxide 19 regions.
Still with reference to FIG. 2, the region 12 of electric continuity and the channel region 31 (shown in FIG. 1) are bounded, laterally along their widths, by a thick field oxide layer 32.
Shown in FIG. 3 are the masks employed to form the memory cell 1. In detail, the reference numeral 4 denotes a capacitive implant mask for forming the region 12 of electric continuity, and the reference numeral 5 denotes a tunnel mask for forming the region 19.
Further in FIG. 3, the reference numeral 6 denotes a self-aligned etching mask (to be explained hereinafter), and the reference numeral 7 denotes a drain/source implant mask for forming the drain/source region 13. Finally, the reference numeral 8 denotes a mask for making the drain contact D for the select transistor 3.
The process for fabricating the memory cell 1 is a typical (two- or single-well) CMOS process.
Referring first to FIG. 4, and starting from the substrate 10, the capacitive implant mask 4 is formed after growing the field oxide 32, not shown in the Figure, to bound the active areas of the device 2 and grow a sacrifical oxide layer 39. This mask is formed using a layer 40 of a light-sensitive material fully covering the sacrificial oxide layer 39 but for a window 41 through which the capacitive implantation (usually phosphorus for N-channel cells) will be effected to form the region 12 of electric continuity, as shown in FIG. 5.
Referring now to FIG. 5, after removing the mask 4 and sacrificial oxide layer 39, a gate oxide layer 42 is grown to form the gate oxide region 18 of the cell 1. The tunnel mask 5 is then deposited which comprises a layer 43 of a light-sensitive material fully covering the gate oxide layer 42 but for a window 45 where the thin tunnel oxide region 19 is to be formed.
Thereafter, a dedicated etching is applied to cleanse the surface 15, which results in the exposed portion of the layer 42 being etched away and the intermediate structure shown in FIG. 5 being produced.
Referring to FIG. 6, the thin tunnel oxide region 19 surrounded by the gate oxide layer 42 is grown using the tunnel mask 5. The tunnel mask 5 is then removed to provide the intermediate pattern shown in FIG. 6. This is followed by the steps of:
depositing and doping the first (poly) layer 44 of polycrystalline silicon, as shown in FIG. 7; PA1 shaping layer 44 to delimit the width (along the horizontal direction in FIGS. 2 and 3) of the floating gate region 20 for the cell 1; PA1 depositing the composite ONO (dielectric interpoly 21) layer, and an additional polysilicon layer, the so-called "mini-poly," not shown in FIGS. 1 and 2, since a thermal treatment will integrate it to the second (poly2) layer of polycrystalline silicon yet to be deposited; PA1 back-etching the additional polysilicon layer and the ONO layer 21 in the circuitry area of the device 2; PA1 depositing and doping the poly2 layer; PA1 self-alignment etching the poly2, mini-poly, ONO, poly1, and gate oxide 42 layers in the matrix, using the mask 6 to delimit the length (along the vertical direction in FIG. 3) of the floating gate 20 and control gate 22 regions of the cell 1 and simultaneously back-etching the poly2 and poly1 layers in the circuitry area to define the gates of transistors comprising the circuitry; PA1 growing a protecting oxide layer (not shown because embedded within the dielectric layer 30) over the control gate region 22; PA1 optionally effecting a first light drain/source implantation; PA1 forming oxide portions, or spacers, not shown in the drawings, laterally of the floating gate 20 and control gate 22 regions; and PA1 effecting a drain/source implantation using the mask 7, to produce the regions 11, 13 and 14, and therefore, the structure shown in FIGS. 1 and 2. PA1 Subsequently, the following conventional final steps are carried out: PA1 forming the intermediate dielectric layer 30 and the contacts, and defining the metal; and PA1 depositing the passivation layer.
What is needed is to provide a CMOS process for fabricating memory cells of the FLOTOX EEPROM type with improved potential for scaling.